The present invention relates to programmable coding and decoding arrangements in general, and more particularly to an arrangement of the above type which is situated between and connected to digital and analog telecommunication lines.
In the field of telecommunications, use of digital signalling techniques in transmitting information over long distances is gaining more and more prominence, even for audio transmission. On the other hand, the subscriber lines between the central office or local exchange and the subscriber equipment are usually operated in an analog fashion. Therefore, it is necessary to interpose a coding and decoding arrangement between the digitally operated main lines and the analog subscriber lines. Such coding and decoding arrangements perform digital filtering, analog-to-digital and digital-to-analog conversion, and often also echo suppression operations. Each of the coding and decoding arrangements of the above type typically includes a plurality of signal processing components which perform the above-mentioned tasks and which are usually arranged in two separate paths, one for the processing of the incoming signals, and one for the processing of the outgoing signals.
With an increased sophistication of the coding and decoding arrangements, there is an increasing need for testing the preformance of the various signal processing components, so as to assure proper functioning of the arrangement. So, for instance, there are already known arrangements of the above type in which it is possible to set the digital filter coefficients in dependence on the conditions prevailing in the subscriber line, on the signal strength or on other parameters. In this manner, the transfer functions of the digital filters may be changed when the above parameters change and thereby the quality of the message signal rendition is improved. Under such circumstances, it is desirable to be able not only to test the components for their integrity and performance of their intended function, but also to determine the instantaneous values of the coefficients. For this reason, there have already been developed various testing arrangements of greater or lesser sophistication for use in testing the coding and decoding arrangements. However, experience with these conventional testing arrangements has shown that they are either too complex and hence expensive, requiring a substantial amount of additional hardware outside the semiconductor chip carrying the coding and decoding arrangement, or do not perform all of the testing and information gathering tasks which are needed for assuring satisfactory performance of the coding and decoding arrangement.